POETS (Partial Ordered Event Triggered Systems) technology is based on the idea of an extremely large number of small cores, embedded in a fast, hardware, parallel communications infrastructure - the core mesh. Inter-core communication is effected by small, fixed size, hardware data packets (a few bytes) - aka messages.
The POETS project describes research to investigate and prototype a software methodology and associated hardware platform to realise the potential of this architecture.
The physical implementation of such a system imposes a fixed and finite topology on the core graph, but a thin (hardware) layer on top of the cores allows the user to virtualise an arbitrary connectivity graph on top of the physical one. Once this is done, the mapping of problem domain to processor mesh follows naturally.
For more information about the POETS project, please download the POETS Project Partner Precis document.